The present invention relates to a well voltage setting circuit for erasing a nonvolatile semiconductor memory and, in particular, to a nonvolatile semiconductor memory well voltage setting circuit capable of preventing latch-up during erase of a nonvolatile semiconductor memory that uses a channel erase system and a semiconductor memory device provided with the circuit.
Conventionally, there has been an ETOX (registered trademark of Intel) type flash memory cell as a flash memory used most generally. FIG. 12 shows a schematic sectional view of this ETOX type flash memory cell. In this ETOX type flash memory cell, a floating gate 103 is formed on a substrate 108 located between a source 106 and a drain 107 via a tunnel oxide film 105, and a control gate 101 is further formed via a layer insulation film 102.
The principle of operation of this ETOX type flash memory cell will be described next. In this memory cell, according to voltage conditions shown in Table 1, during write, a voltage Vpp (10 V, for example) is applied to the control gate 101, a reference voltage Vss (0 V, for example) is applied to the source 106, and a voltage of 6 V is applied to the drain 107.
With this arrangement, a large amount of current flows through the channel region to generate hot electrons in a portion on the drain side where the electric field is high. The electrons are injected into the floating gate 103 to raise a threshold voltage of this memory cell. The distribution state of the raised threshold voltage is shown in FIG. 13. In FIG. 13, the vertical axis represents the number N of memory cells, and the horizontal axis represents the threshold voltage of the memory cells.
In erase operation, a voltage Vnn (xe2x88x929 V, for example) is applied to the control gate 101, and a voltage Vpe (4 V, for example) is applied to the source 106, so as to extract electrons from the floating gate 103 on the source side. Consequently, the threshold voltage of the memory cell is lowered. FIG. 13 also shows the distribution state of the lowered threshold voltage. In this erase operation, a BTBT (Band To Band Tunneling) current flows. Concurrently, hot holes and hot electrons are generated. The hot electrons flow toward the substrate 108. On the other hand, the hot holes are pulled toward the tunnel oxide film 105 to be trapped in the tunnel oxide film 105. This trapping phenomenon degrades reliability.
In read operation of the memory cell, a voltage of 1 V is applied to the drain 107, and a voltage of 5 V is applied to the control gate 101. In this case, when this memory cell is in the erased state, that is, when the threshold voltage is low, a current flows through the cell. By this, the storage information is determined to be xe2x80x9c1xe2x80x9d. When this memory cell is in the programmed state, that is, when the threshold voltage is high, no current flows through the memory cell. By this, the storage information is determined to be xe2x80x9c0xe2x80x9d.
In the ETOX type flash memory cell, as described above, there is a problem that the BTBT current generated on the source side in the erase operation deteriorates the reliability of the memory cell.
As a means for solving this problem, there is a method for using channel erase that causes no BTBT current during the erase operation. This method is disclosed in Japanese Patent Laid-Open Publication No. HEI 11-39890. The write and read operations of this method are similar to those of the aforementioned source side erase system.
FIG. 14 shows the operational principle of this channel erase system. As shown in FIG. 14, in erase operation, a voltage Vnn (xe2x88x929 V, for example) is applied to a word line connected to a control gate 191 on a layer insulation film 192, and a voltage Vesc (+6 V, for example) is applied to a source 195 and a well 197. The source 195 may be in an OPEN state. By this operation, an intense electric field is applied to a tunnel oxide film 194 located between the channel layer and the floating gate 193, so that electrons are extracted from the floating gate 193 by the FN (Fowler-Nordheim) tunneling phenomenon and the threshold value are lowered. The following Table 2 shows the voltage application conditions in this case.
At this time, a potential (Vp-well) of the well 197 is equal to that of the source 195, and therefore, no electric field is concentrated on a boundary portion between the source 195 and the well 197, so that no BTBT current is generated. Consequently, no hot hole is generated. Therefore, trap of hot holes does not occur in the tunnel oxide film 194, so that the reliability of the memory cell is improved.
Next, FIG. 15 shows in more detail a structural cross-sectional view of the memory cell in which the channel erase system shown in FIG. 14 is put into practice. This structure is called the triple well structure, wherein an N-well 209 is provided so as to electrically separate a substrate 208 from a P-well 204 in which the memory cell is formed.
In this case, a reference voltage (0 V, for example) is applied to the P-substrate 208 so as to put a bit line BL connected to the drain 207 into a floating state. A voltage Vesc (6 V, for example) is further applied to a line CA connected to a contact region 205 connected to the source 206 so as to apply the voltage Vesc to the P-well 204. The common source line CS is a line for commonly connecting together the sources in a block.
Further, a voltage Vnn (xe2x88x929 V, for example) is applied to a control gate 201 via the word line WL connected to the control gate 201, and a voltage Vnw (not lower than 6 V, for example) is applied to the N-well 209.
By this operation, the source 206 and the P-well 204 are made to have same potential, effecting channel erase.
In FIG. 15, the region denoted by the symbol N is an N+ diffusion region and represents a contact region for electrical connection to the N-well 209. Moreover, in FIG. 15, the region denoted by the symbol P is a P+ diffusion region and represents a contact region for electrical connection to the P-well 204.
During erase (also, write and during operations), as drive circuits (drivers) for applying the aforementioned various voltages, there are provided a word line drive circuit for driving the word line WL, a bit line drive circuit for driving the bit line BL, a common source line drive circuit for driving the common source line, an N-well drive circuit and a P-well drive circuit, which are arranged in the peripheral portion of the memory cell array.
Further, in order to supply various voltages to these drive circuits, there are arranged a positive voltage charge pump circuit for generating a positive high voltage from a power voltage through boosting, a negative voltage charge pump circuit for generating oppositely a negative high voltage from the power voltage through boosting, regulator circuits for generating various voltages by deboosting inputs outputted from these charge pump circuits, stabilizing those voltages and outputting the voltages, and so on.
FIG. 16 shows a construction necessary for, in particular, erase among the peripheral circuits of the memory cell array. FIG. 17 shows one block of 64 KB of the memory cell array. These memory cells are formed in one P-well (see FIG. 18).
As shown in FIG. 17, the memory cell array of one block is constructed by a plurality of memory cells MS arranged on the array. The control gates of 512 memory cells MS are connected to this word line WL0, as in the cases with the word lines WL1 through WL1023.
The drains of 1024 memory cells MS are connected to the bit line BL0, as in the cases with the bit lines BL1 through BL511.
The sources of the memory cells MS in an identical block are connected to a common source line SL.
Further, the well portions of the memory cells MS in an identical block are formed in a common P-well, and a voltage is applied from a terminal PW to this common P-well. As shown in FIG. 16, 1024 word line drivers (word line drive circuits) 152 for driving the aforementioned respective word lines WL0 through WL1023 are arranged in the peripheral portion of this memory cell array 153.
When an erase pulse is applied, a voltage Vnn (xe2x88x929 V, for example) outputted from the negative voltage charge pump circuit 151 for generating a negative high voltage from the power voltage through boosting is inputted as a low-potential side voltage to the word line driver 152.
On the other hand, a reference voltage Vss is inputted to a high-potential side voltage line VPX of the word line driver 152. This high-potential side voltage line VPX comes to have a voltage of 10 V during write and comes to have a voltage of 5 V during read, and fixed to the reference voltage Vss when the erase pulse is applied because the operation of the regulator circuit 158 is stopped.
The word line driver 152 is operated by a decoder signal from a decoder circuit (not shown). During write and read, this decoder circuit generates a control signal for applying the control gate voltage shown in the aforementioned Table 2 to the word line sequentially selected during write and read, and during erase, for applying a specified voltage to the word lines selected in blocks or of all the blocks. Moreover, the word line driver 152 is controlled so as to output the reference voltage Vss to the non-selected word lines.
Moreover, an output (8 V, for example, when the erase pulse is applied) from the high-voltage charge pump circuit 160, which generates a positive high voltage from the power voltage through boosting, is stabilized in a regulator circuit 157. The stabilized voltage (6 V, for example, when the erase pulse is applied) obtained by the regulator circuit 157 is supplied to a P-well driver 156 and an N-well driver 155. The P-well driver 156 outputs this voltage to a terminal PW (see FIG. 15), and the N-well driver 155 outputs this voltage to a terminal NW (see FIG. 15).
The block diagram of FIG. 16 does not show the bit line drive circuit for driving the bit line BL and the common source line drive circuit for driving the common source line.
The operation of the drive circuit located on the well side of this channel erase system during erase will be described next. When the erase starts, the negative voltage charge pump 151 operates to output a negative voltage Vnn (xe2x88x929 V, for example) to the word line WL. Moreover, the positive voltage charge pump 160 operates to output a positive voltage (8 V, for example). This charge pump output voltage is formed into a stabilized output of 6 V by the regulator circuit 157 and inputted to the N-well driver 155. The output of the N-well driver 155 comes to have a voltage of 6 V, and a voltage of 6 V is outputted from the terminal NW to an N-well 179 of the memory cell array shown in FIG. 18.
The N-well drive circuit (driver) 155 is constructed by a well-known technology, and no detailed description is herein provided therefor.
Likewise, with regard to the potential of the P-well, the output (8 V, for example) from the positive voltage charge pump circuit 160 is inputted to the regulator circuit 157. The regulator circuit 157 outputs the stabilized output of 6 V which is inputted to the terminal PW. Then, the voltage of 6 V is inputted to a contact region 175 (i.e., P diffusion region) shown in FIG. 18, so that the P-well 174 have a potential of 6 V.
Next, FIG. 19 shows one example of the P-well drive circuit (driver) 156. FIG. 20 shows an example of the construction of the high-voltage level shifter circuit 163 in FIG. 19. In this P-well driver 156, when a voltage of 6 V is applied to a voltage line hhers and an N-MOS transistor 162 is put into an OFF state when a signal erswel comes to have high level (power voltage level or, for example, 5 V). On the other hand, in a high-voltage level shifter circuit 163, a P-MOS transistor 213 and an N-MOS transistor 212 are turned on, and a P-MOS transistor 211 and an N-MOS transistor 214 are turned off. By this operation, L (Low) level (reference voltage Vss, for example) is outputted as an output 216 from the high-voltage level shifter circuit 163, and the P-MOS transistor 161 of FIG. 19 is turned on, making the terminal PW have the potential level (6 V) of the voltage line hhers.
On the other hand, if L level (reference voltage Vss, for example) is inputted as the signal erswel, then the terminal PW comes to have L level (reference voltage Vss, for example).
Next, there will be described a shutdown sequence in which the erase pulse application ends and both the well and word line voltages come to have the reference voltage. If this shutdown sequence is executed, then the signal erswel comes to have L level to turn off the P-MOS transistor 161 and turn on the N-MOS transistor 162. By this operation, the P-well 174 of FIG. 18 is forced to the reference voltage Vss. Further, the word line WL side is also forced to this reference voltage Vss, and finally, the positive voltage charge pump 160 and the negative voltage charge pump 151 are stopped.
FIG. 21 shows one example of the waveforms of the word line voltage and the P-well voltage in the shutdown sequence after the erase pulse application. In FIG. 21, the origin is at the time of the end of the erase pulse application.
As shown in FIG. 21, in accordance with the timing when the P-well 174 of FIG. 18 is forced to the reference voltage Vss, the word line voltage is changed from xe2x88x929 V to about xe2x88x9210 V by further lowering by about 1 V. Subsequently, this word line voltage is slowly forced to 0 V. The reason why the above phenomenon occurs will be described in the order of the matters (1), (2) and (3) as follows:
(1) The reason why the operation of forcing the P-well voltage to the reference voltage Vss is steep,
(2) The reason why the word line voltage is once lowered from xe2x88x929 V to about xe2x88x9210 V,
(3) The reason why the operation of forcing the word line voltage to the reference voltage Vss is dull (broad).
The matter (1) is related to the operation during write. The construction of the memory cell when the channel erase system is used will be described first. As shown in FIG. 18, with regard to the sectional structure of the portion in which the memory cells form an array, each memory cell is formed inside the P-well 174 electrically separated from a P-substrate 178 by the N-well 179. In FIG. 18 are shown a control gate 171, a floating gate 172, contact regions 173 and 175, a source 176 and a drain 177, and the word line WL is connected to the control gate 171.
The triple well structure is the structure required for applying a positive voltage (6 V, for example) to the P-well 174 during erase. Therefore, the memory cell that exists in the P-well 174 is a memory cell of one block (64 KB, for example) erased through batch erase. In this case, a terminal for supplying a voltage to the P-well 174 is arranged only in the peripheral portion inside the memory cell array. In the normal case, the P-well 174 is electrically connected to the substrate 178.
During write, a large amount of current (for example, 500 xcexcA per cell) flows through the channel to execute program as described above. At this time, a current (for example, 100 xcexcA per cell) also flows on the substrate 178 side at the same time. Therefore, when this program is concurrently executed with, for example, eight bits, the current that flows on the substrate 178 side amounts to about 800 xcexcA. This current is to be forced to the reference voltage Vss via the N-MOS transistor 162 of the P-well driver shown in FIG. 19.
In this case, it is required to reliably force the potential of the P-well 174 to the reference voltage Vss. Therefore, a comparatively large size is needed as the transistor size in order to secure a great current drawing capacity. For example, the channel width is minimized on the design rule, and the channel width W is widened so that W=100 xcexcm. As a result, in the shutdown sequence during erase, the voltage of the P-well 174 is discharged through this N-MOS transistor 162. This is the reason why the P-well voltage comes to have a steep waveform as shown in FIG. 21.
The reason why the word line voltage is once lowered as shown in FIG. 21 according to the aforementioned matter (2) will be described next. When the P-well 174 is sharply forced from 6 V to the reference voltage Vss by the capacitive coupling of the word line WL with the P-well 174, the word line voltage changes from, for example, xe2x88x929 V to a further negative voltage of xe2x88x9210 V. FIG. 22 shows an equivalent circuit diagram of this capacitive coupling. For example, in one block (64 KB) of a flash memory cell array that has a minimum processing level of, for example, 0.25 xcexcm, a capacitance Cww becomes:
0.7 fFxc3x9764xc3x978xc3x971024=367 pF
which is very large. Therefore, the coupling ratio also becomes great. Consequently, as shown in FIG. 21, the word line voltage is lowered from xe2x88x929 V to xe2x88x9210 V in the shutdown sequence.
The reason why the forcing of the word line voltage to the reference voltage Vss is broad according to the aforementioned matter (3) will be described next. Normally, the word line drive circuit (driver) for driving the word line WL is to drive one word line. Therefore, as shown in FIG. 23, output-stage transistors 221 and 222 of the word line driver have a load smaller than that of the P-well driver that is required to fix the well potential, or a large capacitive load. Therefore, the driving capacity of the word line driver is not required to be as large as that of the P-well driver.
Furthermore, since each of the word line drivers is connected to one word line, it is required to arrange a large number of the word line drivers. This becomes a factor for increasing the layout area, and therefore, the output stage transistor of the word line driver is restrained to a comparatively small size.
Consequently, as shown in FIG. 21, the word line voltage after the erase pulse application is slowly i.e. broadly forced from xe2x88x929 V to the reference voltage Vss.
It is to be noted that the small driving capacity of the output-stage transistor 222 of the word line driver shown in FIG. 23 is attributed to the capacitive coupling as shown in FIG. 21 and also leads to the susceptibility of the word line to voltage fluctuations with respect to the swift movement of the P-well voltage.
The point that the aforementioned matter (2) occurring in the prior art example poses a problem will be described below.
As shown in FIG. 23 described hereinabove, the word line driver 152 has a non-inversion type high-voltage level shifter circuit 223, and the gates of the P-MOS transistor 221 and the N-MOS transistor 222 are connected to the output of the circuit. The source and the N-well (not shown) of this P-MOS transistor 221 are connected to a voltage line VPX. This voltage line VPX, which comes to have a voltage of 10 V during write and have a voltage of 5 V during read, comes to have the reference voltage Vss during erase as a consequence of the stop of the regulator circuit 158 shown in FIG. 16.
On the other hand, the source and the P-well of the N-MOS transistor 222 are connected to a voltage line Vnn. This voltage line Vnn, which comes to have a voltage of xe2x88x929 V during erase, has the reference voltage Vss during write and read as a consequence of the stop of the regulator circuit 157 shown in FIG. 16. Then, the drains of these transistors 221 and 222 are connected together to the word line WL.
It is to be noted that the non-inversion type high-voltage level shifter circuit 223 converts the level of a decoding signal DWL from a decoding circuit (not shown) into a voltage signal level across the reference voltage and Vnn in a non-inversion manner during erase. This decoding signal DWL is a signal of a voltage level across the power voltage and the reference voltage.
A problem that occurs in the N-MOS transistor 222 of this word line driver 152 will be described next with reference to FIG. 24. The source 184 and the P-well 186 of this N-MOS transistor 222 have a voltage Vnn (xe2x88x929 V), while the gate 181 receives the output (reference voltage Vss in this case) from the non-inversion type high-voltage level shifter circuit 223 and is put in the ON state. To the word line WL connected to the drain 185 of this N-MOS transistor 222 is outputted a voltage of xe2x88x929 V.
In FIG. 24, the symbol P denotes a P+ diffusion region, which is a contact region 183 for supplying a voltage to the P-well 186. Further, the symbol N denotes an N+ diffusion region, which forms the regions of a source 184 or a drain 185. Moreover, the symbol N in the N-well 187 is an N+ diffusion region, which is a contact region for supplying a voltage to the N-well 187.
When the erase pulse application ends and the system operation enters the shutdown sequence, there is a case where the word line voltage temporarily drops from xe2x88x929 V to, for example, xe2x88x9210 V as shown in FIG. 21.
As described above, if there occurs a state in which the potential (xe2x88x929 V) of the P-well 186 goes beyond a built-in voltage (0.6 V) with respect to the potential (xe2x88x9210 V) of the drain 185 connected to the word line WL, then a forward bias occurs in the PN junction portion, and a current flows from the P-well 186 to the drain 185.
If, for example, the P-well 186 has a voltage of xe2x88x929 V and the drain 185 comes to have a voltage of not higher than xe2x88x929.6 V, then the forward bias occurs between the drain 185 and the P-well 186, and a current flows. If a current flows due to the forward bias, then this operates as a trigger to cause local latch-up. If this latch-up occurs, then a malfunction occurs, and this may leads to the destruction of the flash memory in the worst case.
Accordingly, an object of the present invention is to provide a well voltage setting circuit of a nonvolatile semiconductor memory capable of preventing the aforementioned latch-up in the shutdown sequence after erase pulse application when channel erase is executed in a flash memory and a semiconductor memory device provided with the well voltage setting circuit.
In order to achieve the aforementioned objective, the present invention provides a well voltage setting circuit of a nonvolatile semiconductor memory, comprising:
floating-gate field-effect transistors able to electrically write and erase information, the floating-gate field-effect transistors being each provided with a control gate, a floating gate, a drain and a source, and arranged in rows and columns into a block to form a memory cell array;
a plurality of row lines each connected to control gates of the floating-gate field-effect transistors in each row;
a plurality of column lines each connected to drains of the floating-gate field-effect transistors in each column;
a source line connected commonly to sources of the floating-gate field-effect transistors in the block;
a first voltage supply circuit for applying a first voltage to a well which constitutes each of channel regions in arrangement of the memory cell array to be erased when an erase pulse is applied to the memory cell array in an erase operation wherein information of the memory cell array is erased on a block basis by channel erase using a Fowler-Nordheim tunneling phenomenon;
a second voltage supply circuit for applying a reference voltage to the well when the erase pulse application ends; and
a third voltage supply circuit for applying the reference voltage to the well during write and during read.
According to the well voltage setting circuit of this invention, the first voltage supply circuit supplies the first voltage to the well when the erase pulse is applied, and the second voltage supply circuit applies the reference voltage to the well when this erase pulse application ends. Moreover, during write and during read, the third voltage supply circuit applies the reference voltage to the well.
As described above, according to this invention, the reference voltage is supplied to the well by the second voltage supply circuit when the erase pulse application ends, and the third voltage supply circuit applies the reference voltage to the well during write and during read.
Therefore, the capacity of this second voltage supply circuit is set to the capacity appropriate for supplying the reference voltage to the well when the erase pulse application ends, while the capacity of the third voltage supply circuit can be set to the capacity appropriate for supplying the reference voltage to the well during write and during read. With the above capacity setting of the second and third voltage supply circuits, it is enabled to prevent the reduction in the word line voltage attributed to the capacitive coupling of the well with the word line and prevent the latch-up attributed to the forward bias during erase in the word line driver.
In one embodiment of the present invention,
the first voltage supply circuit is constructed of a P-MOS transistor, and
the second and third voltage supply circuits are each constructed of an N-MOS transistor.
According to this embodiment, since the first voltage supply circuit is constructed of a P-MOS transistor, and the second and third voltage supply circuits are each constructed of an N-MOS transistor, there are easily constructed the first voltage supply circuit that applies the first voltage to the well when the erase pulse is applied, the second voltage supply circuit that applies the reference voltage to the well after the erase pulse application and the third voltage supply circuit that applies the reference voltage to the well during write and read.
In one embodiment of the present invention,
the second voltage supply circuit has a current supply capacity smaller than that of the third voltage supply circuit.
According to this embodiment, the second voltage supply circuit more slowly forces the well to the reference voltage than the third voltage supply circuit after the first voltage supply circuit applies the first voltage to the well. With this arrangement, it is enabled to prevent the reduction in the word line voltage attributed to the capacitive coupling of the well with the word line and to prevent the latch-up attributed to the forward bias during erase in the word line driver.
In one embodiment of the present invention, the nonvolatile semiconductor memory well voltage setting circuit further comprises a gate control circuit for controlling a gate of the N-MOS transistor of the second voltage supply circuit, wherein
the gate control circuit is set so that the gate of the N-MOS transistor of the second voltage supply circuit needs a time of not shorter than 100 nanoseconds at a rise of the voltage thereof.
According to this embodiment, in the above gate control circuit, the gate of the N-MOS transistor of the second voltage supply circuit is set so as to require a time of not shorter than 100 nanoseconds at the rise of the voltage. Therefore, the N-MOS transistor of the second voltage supply circuit slowly leads the well to the reference potential, prevents the reduction in the word line voltage attributed to the capacitive coupling of the well with the word line and prevents the latch-up attributed to the forward bias during erase in the word line driver.
The present invention also provides a well voltage setting circuit of a nonvolatile semiconductor memory, comprising:
floating-gate field-effect transistors able to electrically write and erase information, the floating-gate field-effect transistors being each provided with a control gate, a floating gate, a drain and a source, and arranged in rows and columns into a block to form a memory cell array;
a plurality of row lines each connected to control gates of the floating-gate field-effect transistors in each row;
a plurality of column lines each connected to drains of the floating-gate field-effect transistors in each column;
a source line connected commonly to sources of the floating-gate field-effect transistors in the block;
a first voltage supply circuit for applying a first voltage to a well which constitutes each of channel regions in arrangement of the memory cell array to be erased when an erase pulse is applied to the memory cell array in an erase operation wherein information of the memory cell array is erased on a block basis by channel erase using a Fowler-Nordheim tunneling phenomenon, wherein the first voltage supply circuit is constituted of a P-MOS transistor;
a second voltage supply circuit for applying a reference voltage to the well when the erase pulse application ends and during write and during read, wherein the second voltage supply circuit is constituted of an N-MOS transistor; and
a control circuit for controlling the second voltage supply circuit, the control circuit being constituted of a level shifter to apply a voltage lower than a power voltage to a gate of the N-MOS transistor in turning on the N-MOS transistor of the second voltage supply circuit when the erase pulse application ends and to apply a voltage higher than the power voltage to the gate of the N-MOS transistor in turning on the N-MOS transistor of the second voltage supply circuit during write and during read.
In this invention, the control circuit that controls the second voltage supply circuit is constructed of the level shifter to apply a voltage lower than the power voltage to the gate of the N-MOS transistor when the N-MOS transistor of this second voltage supply circuit is turned on at the end of the erase pulse application and apply a voltage higher than the power voltage to the gate of the N-MOS transistor when the N-MOS transistor of this second voltage supply circuit is turned on during write and during read.
Therefore, the N-MOS transistor of the second voltage supply circuit comes to have a small capacity in the shutdown sequence after the erase pulse application as compared with the capacity thereof during write and during read, and the well can be slowly brought closer to the reference voltage. Therefore, it is enabled to prevent the reduction in the word line voltage attributed to the capacitive coupling of the well with the word line and prevent the latch-up attributed to the forward bias during erase in the word line driver.
The present invention further provides a well voltage setting circuit of a nonvolatile semiconductor memory, comprising:
floating-gate field-effect transistors able to electrically write and erase information, the floating-gate field-effect transistors being each provided with a control gate, a floating gate, a drain and a source, and arranged in rows and columns into a block to form a memory cell array;
a plurality of row lines each connected to control gates of the floating-gate field-effect transistors in each row;
a plurality of column lines each connected to drains of the floating-gate field-effect transistors in each column;
a source line connected commonly to sources of the floating-gate field-effect transistors in the block;
a first voltage supply circuit for applying a first voltage to a well which constitutes each of channel regions in arrangement of the memory cell array to be erased when an erase pulse is applied to the memory cell array in an erase operation wherein information of the memory cell array is erased on a block basis by channel erase using a Fowler-Nordheim tunneling phenomenon;
a second voltage supply circuit for applying a reference voltage to the well after the erase pulse application and during write and during read; and
a fourth voltage supply circuit whose capacity for supplying the reference voltage to an input power line of the second voltage supply circuit is made smaller than the capacity thereof during write and during read in a shutdown sequence after the erase pulse application.
In this invention, the fourth voltage supply circuit comes to have a smaller capacity to supply the reference voltage to the input power line of the second voltage supply circuit than the capacity thereof during write and during read in the shutdown sequence after the erase pulse application. Therefore, the second voltage supply circuit comes to have a smaller capacity than the capacity thereof during write and during read in the shutdown sequence after the erase pulse application, and the well can be slowly brought closer to the reference voltage. Therefore, it is enabled to prevent the reduction in the word line voltage attributed to the capacitive coupling of the well with the word line and prevent the latch-up attributed to the forward bias during erase in the word line driver.
In one embodiment of the present invention,
the fourth voltage supply circuit is constituted of a resistor equivalent element and a first N-MOS transistor
to supply a voltage for applying the reference voltage to the well through only the resistor equivalent element to the input power line of the second voltage supply circuit after the erase pulse application by the first voltage supply circuit, and
to supply a voltage for applying the reference voltage to the well to the input power line of the second voltage supply circuit through the first N-MOS transistor and the resistor equivalent element by turning on the first N-MOS transistor during read and during write.
In this embodiment, the fourth voltage supply circuit is constructed of the resistor equivalent element and the first N-MOS transistor and supplies the voltage for applying the reference voltage to the well to the input power line of the second voltage supply circuit only through the resistor equivalent element after the erase pulse application by the first voltage supply circuit. Therefore, the second voltage supply circuit comes to have a smaller capacity than the capacity thereof during write and during read in the shutdown sequence after the erase pulse application, and the well can be slowly brought closer to the reference voltage. Therefore, it is enabled to prevent the reduction in the word line voltage attributed to the capacitive coupling of the well with the word line and prevent the latch-up attributed to the forward bias during erase in the word line driver.
In one embodiment of the present invention,
the fourth voltage supply circuit is constituted of a first N-MOS transistor and a second N-MOS transistor
to supply a voltage for applying the reference voltage to the well through the second N-MOS transistor whose gate voltage is the power voltage to the input power line of the second voltage supply circuit after the erase pulse application by the first voltage supply circuit, and
to supply a voltage for applying the reference voltage to the well to the input power line of the second voltage supply circuit by concurrently turning on the first N-MOS transistor during read and during write.
In this embodiment, the fourth voltage supply circuit is constructed of the first N-MOS transistor and the second N-MOS transistor and supplies the voltage for applying the reference voltage to the well to the input power line of the second voltage supply circuit through the second N-MOS transistor whose gate voltage is the power voltage after the erase pulse application by the first voltage supply circuit. Moreover, the fourth voltage supply circuit turns on the first N-MOS transistor together with the second N-MOS transistor during read and during write to supply the voltage for applying the reference voltage to the well to the input power line of the second voltage supply circuit.
Therefore, according to this embodiment, the second voltage supply circuit comes to have a smaller capacity than the capacity thereof during write and during read in the shutdown sequence after the erase pulse application, and the well can be slowly brought closer to the reference voltage. Therefore, it is enabled to prevent the reduction in the word line voltage attributed to the capacitive coupling of the well with the word line and prevent the latch-up attributed to the forward bias during erase in the word line driver.
The present invention still further provides a well voltage setting circuit of a nonvolatile semiconductor memory, comprising:
floating-gate field-effect transistors able to electrically write and erase information, the floating-gate field-effect transistors being each provided with a control gate, a floating gate, a drain and a source, and arranged in rows and columns into a block to form a memory cell array;
a plurality of row lines each connected to control gates of the floating-gate field-effect transistors in each row;
a plurality of column lines each connected to drains of the floating-gate field-effect transistors in each column;
a source line connected commonly to sources of the floating-gate field-effect transistors in the block;
a first voltage supply circuit for applying a first voltage to a well which constitutes each of channel regions in arrangement of the memory cell array to be erased when an erase pulse is applied to the memory cell array in an erase operation wherein information of the memory cell array is erased on a block basis by channel erase using a Fowler-Nordheim tunneling phenomenon;
a second voltage supply circuit for applying a reference voltage to the well after the erase pulse application and during write and during read;
an intermediate voltage supply circuit for supplying an intermediate voltage for making the potential of the well once have an intermediate level between a potential when the erase pulse is applied and the reference voltage to an input power line of the second voltage supply circuit after the erase pulse application by the first voltage supply circuit; and
a reference voltage supply circuit for making the potential of the well have the intermediate level by the intermediate voltage supply circuit and thereafter applying the reference voltage to the input power line of the second voltage supply circuit in a shutdown sequence after the erase pulse application.
In this invention, the intermediate voltage supply circuit supplies the intermediate voltage to the input power line of the second voltage supply circuit after the erase pulse application by the first voltage supply circuit, making the well voltage once have the level between the potential when the erase pulse is applied and the reference voltage and thereafter applying the reference voltage to the well from the second voltage supply circuit by the reference voltage supply circuit.
Therefore, the well can be more slowly brought closer to the reference voltage in the shutdown sequence after the erase pulse application than in the write and read stages. Therefore, it is enabled to prevent the reduction in the word line voltage attributed to the capacitive coupling of the well with the word line and prevent the latch-up attributed to the forward bias during erase in the word line driver.
In one embodiment of the present invention, the nonvolatile semiconductor memory device comprises therein the well voltage setting circuit stated above.
In this embodiment, there can be provided a nonvolatile semiconductor memory device capable of preventing the reduction in the word line voltage attributed to the capacitive coupling of the well with the word line and preventing the latch-up attributed to the forward bias during erase in the word line driver by virtue of the built-in well voltage setting circuit.